Parallel Logic Simulation of Digital Circuits Abstract Parallel Logic Simulation of Digital Circuits

Parallel Logic Simulation of Digital Circuits By Hong Kyu Kim Parallel discrete event simulation (PDES) is e cient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments were performed to demonstrate that the two proposed techniques together provide signi cant reduction in parallel simulation time. Unlike most other partitioning algorithms, the proposed partitioning algorithm preserves circuit concurrency by assigning circuit gates that can be evaluated at about the same time to di erent processors. As a result, the concurrency preserving partitioning (CPP) algorithm can provide instantaneous load balancing, instead of only aggregated load balancing, throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. In addition, a new concurrency metric is proposed to evaluate partitioning algorithms before the execution of parallel simulations. Even though PDES can reduce the logic simulation time for large circuits considerably, it generates more events than necessary for certain high activity circuits and produces inconsistent speedup over di erent circuits. The proposed Event Lookahead Time Warp (ETW) algorithm can look ahead and combine and execute multiple events at each gate optimistically so that the probability of unnecessary events can be reduced. As a result, it can reduce rollback cost, obtain better load balance, and achieve more consistent execution times and reasonable speedups.